High-Density Memristor-CMOS Ternary Logic Family

This paper presents the first experimental demonstration of a ternary memristor-CMOS logic family. We systematically design, simulate and experimentally verify primitive functions: AND, OR NOT gates. These are then used to build combinational NAND, NOR, XOR XNOR gates, as well data handling MAX MIN Our simulations performed using 50-nm process which verified with in-house fabricated indium-tin-oxide memristors, optimized for fast switching, high transconductance, low current leakage. obtain close an order magnitude improvement in density over conventional CMOS logic, reduction switching speed by factor 13 prior state-of-the-art memristor results. anticipate extensions this work can realize practical implementation where is critical importance.